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regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
m37906f8cfp, M37906F8CSP preliminar y notice: this is not a final specification. som e param etric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers description these are single-chip 16-bit microcomputers designed with high-per- formance cmos silicon gate technology, including the internal flash memory and being packaged in 42-pin plastic molded ssop or shrink plastic molded dip. these microcomputers support the 7900 series instruction set, which are enhanced and expanded instruction set and are upper-compatible with the 7700/7751 series instruction set. the cpu of these microcomputers is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing. also, the bus interface unit of these microcomputers enhances the memory access efficiency to execute instructions fast. therefore, these mi- crocomputers are suitable for office, business, and industrial equip- ment controller that require high-speed processing of large data. also, they are suitable for motor-control equipment since each of them includes the motor control circuit. for the internal flash memory, single-power-supply programming and erasure, using a prom programmer or the control by the cen- tral processing unit (cpu), is supported. also, each of these micro- computers has the memory area dedicated for storing a certain software which controls programming and erasure (reprogramming control software). therefore, on these microcomputers, the program can easily be changed even after they are mounted on the board. distinctive features number of basic machine instructions .................................... 203 memory flash memory (user rom area) ................................... 60 kbytes ram ............................................................................. 3072 bytes flash memory (boot rom area) ..................................... 8 kbytes instruction execution time the fastest instruction at 20 mhz frequency ........................ 50 ns single power supply .................................................... 5 v ?0.5 v interrupts ........... 5 external sources, 21 internal sources, 7 levels multi-functional 16-bit timer ................................................. 10 + 3 (three-phase motor drive waveform or pulse motor drive waveform output is available.) serial i/o (uart or clock synchronous) ..................................... 2 10-bit a-d converter ............................................ 5-channel inputs 8-bit d-a converter ............................................ 2-channel outputs 12-bit watchdog timer programmable input/output (ports p1, p2, p5, p6, p7) ............. 30 power supply voltage .................................................. 5 v ?0.5 v programming/erase voltage ........................................ 5 v ?0.5 v programming method .................... programming in a unit of word erase method ............................................ block erase or total erase m37906f8cfp, M37906F8CSP ............... 4 blocks (8 kbytes ? 2, 16 kbytes ? 1, 28 kbytes ? 1) programming/erase control by software command maximum number of reprograms ............................................ 100 application control devices for office equipment such as copiers and facsimiles control devices for industrial equipment such as communication and measuring instruments control devices for equipment, requiring motor control, such as inverter air conditioners and general-purpose inverters
m37906f8cfp, M37906F8CSP preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 2 p7 0 /an 0 p7 1 /an 1 p7 2 /an 2 p7 3 /an 3 /da 0 av ss p7 4 /an 4 /da 1 /int 3 /rtp trg0 v ref p1 0 /cts 0 /rts 0 p1 1 /cts 0 /clk 0 p1 4 /cts 1 /rts 1 p2 0 /ta4 out p2 1 /ta4 in p2 2 /ta9 out p2 3 /ta9 in p2 5 (/tb1 in ) p2 6 (/tb2 in ) p2 7 (/int 3 /rtp trg0 ) md1 x out p2 4 (/tb0 in ) p1 5 /cts 1 /clk 1 p1 6 /rxd 1 av cc p1 2 /rxd 0 p1 3 /txd 0 p1 7 /txd 1 40 41 42 22 23 24 25 26 27 28 29 30 31 32 34 35 36 37 38 39 33 3 2 1 21 20 19 18 17 16 15 14 13 12 11 9 8 7 6 5 4 10 x in v ss p6 5 /ta2 in /u/rtp1 1 p6 4 /ta2 out /v/rtp1 0 p6 3 /ta1 in /w/rtp0 3 p6 2 /ta1 out /u/rtp0 2 p6 1 /ta0 in /v/rtp0 1 p6 0 /ta0 out /w/rtp0 0 p5 7 /int 7 /tb2 in /idu p5 6 /int 6 /tb1 in /idv p5 5 /int 5 /tb0 in /idw md0 v cont reset m37906f8cfp p6out cut /int 4 v cc (note) (note) (note) m37906f8cfp pin configuration (top view) outline 42p2r-e note: allocation of pins tb0 in to tb2 in and int 3 /rtp trg0 can be switch- ed by software.
3 m37906f8cfp, M37906F8CSP preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers M37906F8CSP pin configuration (top view) outline 42p4b p7 0 /an 0 p7 1 /an 1 p7 2 /an 2 p7 3 /an 3 /da 0 av ss p7 4 /an 4 /da 1 /int 3 /rtp trg0 v ref p1 0 /cts 0 /rts 0 p1 1 /cts 0 /clk 0 p1 4 /cts 1 /rts 1 p2 0 /ta4 out p2 1 /ta4 in p2 2 /ta9 out p2 3 /ta9 in p2 5 (/tb1 in ) p2 6 (/tb2 in ) p2 7 (/int 3 /rtp trg0 ) md1 x out p2 4 (/tb0 in ) p1 5 /cts 1 /clk 1 p1 6 /rxd 1 av cc p1 2 /rxd 0 p1 3 /txd 0 p1 7 /txd 1 40 41 42 22 23 24 25 26 27 28 29 30 31 32 34 35 36 37 38 39 33 3 2 1 21 20 19 18 17 16 15 14 13 12 11 9 8 7 6 5 4 10 x in v ss p6 5 /ta2 in /u/rtp1 1 p6 4 /ta2 out /v/rtp1 0 p6 3 /ta1 in /w/rtp0 3 p6 2 /ta1 out /u/rtp0 2 p6 1 /ta0 in /v/rtp0 1 p6 0 /ta0 out /w/rtp0 0 p5 7 /int 7 /tb2 in /idu p5 6 /int 6 /tb1 in /idv p5 5 /int 5 /tb0 in /idw md0 v cont reset M37906F8CSP p6out cut /int 4 v cc (note) (note) (note) note: allocation of pins tb0 in to tb2 in and int 3 /rtp trg0 can be switch- ed by software.
m37906f8cfp, M37906F8CSP preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 4 data bank register dt (8) program counter pc (16) incrementer/decrementer (24) program bank register pg (8) input buffer register ib (16) direct page register dpr0 (16) stack pointer s (16) index register y (16) index register x (16) arithmetic logic unit (16) accumulator b (16) accumulator a (16) instruction register (8) central processing unit (cpu) incrementer (24) program address register pa (24) data address register da (24) bus interface unit (biu) reset md1 reference voltage input v ref (0v) av ss avcc vcc clock generating circuit clock input x in v cont x out data buffer dq 0 (8) instruction queue buffer q 0 (8) data bus (odd) address bus a-d converter (10) uart1 (9) uart0 (9) watchdog timer timer tb1 (16) timer tb2 (16) timer tb0 (16) d-a 1 converter (8) timer ta1 (16) timer ta2 (16) timer ta3 (16) timer ta4 (16) timer ta0 (16) ram 3072 bytes p5(3) input/output port p5 p2(8) input/output port p2 p6(6) input/output port p6 p1(8) input/output port p1 p7(5) input/output port p7 md0 (0v) vss processor status register ps (11) p6out cut flash memory 60 kbytes d-a 0 converter (8) data bus (even) data buffer dq 1 (8) data buffer dq 2 (8) data buffer dq 3 (8) instruction queue buffer q 1 (8) instruction queue buffer q 2 (8) instruction queue buffer q 3 (8) instruction queue buffer q 4 (8) instruction queue buffer q 5 (8) instruction queue buffer q 6 (8) instruction queue buffer q 7 (8) instruction queue buffer q 8 (8) instruction queue buffer q 9 (8) direct page register dpr1 (16) direct page register dpr2 (16) direct page register dpr3 (16) clock output reset input timer ta6 (16) timer ta7 (16) timer ta8 (16) timer ta9 (16) timer ta5 (16) block diagram
5 m37906f8cfp, M37906F8CSP preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers memory expansion operating ambient temperature range device structure package ports input/output characteristics power supply voltage power dissipation number of basic machine instructions instruction execution time external clock input frequency f(x in ) system clock input frequency f(f sys ) memory size programmable input/output ports multi-functional timers serial i/o a-d converter d-a converter dead-time timer watchdog timer interrupts clock generating circuit pll frequency multiplier flash memory (user rom area) ram flash memory (boot rom area) p1, p2 p5 p6 p7 ta0 ta9 tb0 tb2 uart0 and uart1 functions (microcomputer mode) functions parameter input/output withstand voltage output current maskable interrups non-maskable interrups 203 50 ns (the fastest instruction at f(f sys ) = 20 mhz) 20 mhz (max.) 20 mhz (max.) 60 kbytes 3072 bytes 8 kbytes 8-bit ? 2 3-bit ? 1 6-bit ? 1 5-bit ? 1 16-bit ? 10 16-bit ? 3 (uart or clock synchronous serial i/o) ? 2 10-bit successive approximation method ? 1 (5 channels) 8-bit ? 2 8-bit ? 3 12-bit ? 1 5 external sources, 18 internal sources. each interrupt can be set to a priority level within the range of 0 7 by software. 3 internal sources incorporated (externally connected to a ceramic resonator or quartz-crystal resonator). the following multiplication ratios are available: ? 2, ? 3, ? 4 5 v0.5 v 125 mw (at f(f sys ) = 20 mhz, typ.; the pll frequency multiplier is inactive.) 5 v 5 ma not available (single-chip mode only). 20 to 85 c cmos high-performance silicon gate process (note) packages m37906f8cfp 42-pin plastic molded ssop (42p2r-e) M37906F8CSP 42-pin shrink plastic molded dip (42p4b) note:
m37906f8cfp, M37906F8CSP preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 6 power supply voltage programming/erase voltage flash memory mode block division for erasure programming method erase method programming/erase control number of commands maximum number of reprograms user rom area boot rom area flash memory parallel i/o mode flash memory serial i/o mode flash memory cpu reprogramming mode flash memory parallel i/o mode flash memory serial i/o mode flash memory cpu reprogramming mode 5 v0.5 v 5 v0.5 v 3 modes: parallel i/o, serial i/o, and cpu reprogramming modes 4 blocks (8 kbytes ? 2, 16 kbytes ? 1, 28 kbytes ? 1); total of 60 kbytes 1 block (8 kbytes ? 1) (note) programmed per word user rom area + boot rom area user rom area user rom area total erase/block erase user rom area + boot rom area user rom area user rom area programming/erase control by software commands 6 commands 100 functions (flash memory mode) functions parameter note: on shipment, our reprogramming control firmware for the flash memory serial i/o mode has been stored into the boot rom area.
7 m37906f8cfp, M37906F8CSP preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers vcc, vss md0 md1 reset x in x out v cont avcc, avss v ref p1 0 p1 7 p2 0 p2 7 p5 0 p5 7 p6 0 p6 5 p7 0 p7 4 p6out cut power supply input md0 md1 reset input clock input clock output filter circuit connection analog power supply input reference voltage input i/o port p1 i/o port p2 i/o port p5 i/o port p6 i/o port p7 p6out cut input input input input input output input i/o i/o i/o i/o i/o input apply 5 v0.5 v to vcc, and 0 v to vss. connect this pin to v ss . connect this pin to vss. the microcomputer is reset when l level is applied to this pin. these are input and output pins of the internal clock generating circuit. connect a ceramic or quartz-crystal oscillator between the x in and x out pins. when an external clock is used, the clock source should be connected to the x in pin, and the x out pin should be left open. when using the pll frequency multiplier, connect this pin to the filter circuit. when not using the pll frequency multiplier, this pin should be left open. power supply input pins for the a-d converter and the d-a converter. connect avcc to vcc, and avss to vss externally. this is the reference voltage input pin for the a-d converter and the d-a converter. port p1 is an 8-bit i/o port. this port has an i/o direction register, and each pin can be programmed for input or output. these pins enter the input mode at reset. these pins also function as i/o port pins of uart0 and uart1. in addition to having the same functions as port p1, these pins also function as i/o pins for timers a4 and a9. by software setting, these pins also function as input pins for timers b0 b2, an input pin for int 3 , and a trigger input pin in the pulse output port mode. in addition to having the same functions as port p1, these pins also function as input pins for int 5 int 7 , input pins for timers b0 b2, and input pins for position- data-input pins in the three-phase waveform mode. in addition to having the same functions as port p1, these pins also function as i/o pins for timers a0 a2, and output pins for the motor drive waveform. in addition to having the same functions as port p1, these pins also function as input pins for the a-d converter. p7 3 functions as an output pin for the d-a converter; p7 4 functions as an output pin for the d-a converter, an input pin for int 3 , and a trigger input pin in the pulse output port mode. this pin has the function to forcibly place port p6 pins in the input mode. also, this pin functions as an input pin for int 4 ; and this pin is used to input a signal, which forcibly cuts off a motor drive waveform output. pin description (microcomputer mode) functions input/ output name pin
m37906f8cfp, M37906F8CSP preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 8 pin description (flash memory serial i/o mode) v cc , v ss md0 md1 _____ reset x in x out avcc, avss v ref p1 0 p1 7 p2 0 p2 3 , p2 7 p2 4 p2 5 p2 6 p6out cut p5 5 p5 7 p6 0 p6 5 p7 0 p7 4 v cont pin power supply input md0 md1 reset input clock input clock output analog supply input reference voltage input input port p1 input port p2 sclk input sda i/o busy output p6out cut input input port p5 input port p6 input port p7 filter circuit connection name input input input input output input input input input i/o output input input input input input /output functions apply 5 v 0.5 v to vcc, and 0 v to vss. connect this pin to vss. connect this pin to vss via a resistor of 10 k ? to 100 k ? . the reset input pin. connect a ceramic oscillator between the x in and x out pins, or input an external clock from the x in pin with the x out pin left open. connect avcc to vcc, and avss to vss. input an arbitrary level within the range of v ss v cc . (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) this is an input pin for a serial clock. this is an i/o pin for serial data. connect this pin to v cc via a resistor (about 1 k ? ). this is an output pin for the busy signal. input h . input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) connect this pin to the filter circuit, or leave this pin open. (this is not used in the flash memory serial i/o mode.)
9 m37906f8cfp, M37906F8CSP preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers basic function blocks each of the m37906f8cfp and M37906F8CSP has the same func- tion as that of the m37906m4c-xxxfp except for the following. therefore, for details except for the following, refer to the datasheet of the m37906m4c-xxxfp. flash memory size ram size memory figure 1 shows the memory map. fig. 1 memory map of m37906f8cfp, M37906F8CSP (single-chip mode) interrupt vector table 000000 16 bank 0 16 00ffff 16 000000 16 000400 16 0000ff 16 00fffe 16 00ffb4 16 internal ram 3072 bytes internal rom 60 kbytes peripheral devices control registers 000fff 16 001000 16 0003ff 16 unused area 00ffb4 16 00ffff 16 timer a6 timer a7 timer a8 timer a9 reserved area reserved area 000000 16 0000ff 16 peripheral devices control registers (see figures 2 and 3.) 000100 16 int 4 a-d conversion reserved area reserved area address matching detect reserved area int 5 int 6 int 7 timer a5 uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 watchdog timer brk instruction zero divide int 3 reserved area reserved area reserved area reserved area reset dbc
m37906f8cfp, M37906F8CSP preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 10 fig. 2 location of sfrs (1) 000000 16 000001 16 000002 16 000003 16 000004 16 000005 16 000006 16 000007 16 000008 16 000009 16 00000a 16 00000b 16 00000c 16 00000d 16 00000e 16 00000f 16 000010 16 000011 16 000012 16 000013 16 000014 16 000015 16 000016 16 000017 16 000018 16 000019 16 00001a 16 00001b 16 00001c 16 00001d 16 00001e 16 00001f 16 000020 16 000021 16 000022 16 000023 16 000024 16 000025 16 000026 16 000027 16 000028 16 000029 16 00002a 16 00002b 16 00002c 16 00002d 16 00002e 16 00002f 16 000030 16 000031 16 000032 16 000033 16 000034 16 000035 16 000036 16 000037 16 000038 16 000039 16 00003a 16 00003b 16 00003c 16 00003d 16 00003e 16 00003f 16 port p2 register reserved area (note) port p1 direction register reserved area (note) port p1 register reserved area (note) port p2 direction register reserved area (note) reserved area (note) port p5 register reserved area (note) port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) a-d control register 0 a-d control register 1 a-d register 0 a-d register 1 a-d register 2 a-d register 3 a-d register 4 reserved area (note) reserved area (note) reserved area (note) uart0 transmit/receive mode register uart0 baud rate register (brg0) uart0 transmit buffer register uart0 transmit/receive control register 1 uart0 receive buffer register uart1 transmit/receive mode register uart1 baud rate register (brg1) uart1 transmit buffer register uart1 transmit/receive control register 0 uart1 transmit/receive control register 1 uart1 receive buffer register address (hexadecimal notation) 000040 16 000041 16 000042 16 000043 16 000044 16 000045 16 000046 16 000047 16 000048 16 000049 16 00004a 16 00004b 16 00004c 16 00004d 16 00004e 16 00004f 16 000050 16 000051 16 000052 16 000053 16 000054 16 000055 16 000056 16 000057 16 000058 16 000059 16 00005a 16 00005b 16 00005c 16 00005d 16 00005e 16 00005f 16 000060 16 000061 16 000062 16 000063 16 000064 16 000065 16 000066 16 000067 16 000068 16 000069 16 00006a 16 00006b 16 00006c 16 00006d 16 00006e 16 00006f 16 000070 16 000071 16 000072 16 000073 16 000074 16 000075 16 000076 16 000077 16 000078 16 000079 16 00007a 16 00007b 16 00007c 16 00007d 16 00007e 16 00007f 16 address (hexadecimal notation) count start register 0 one-shot start register 0 timer a clock division select register timer a0 register timer a1 register timer a2 register timer a3 register timer a4 register timer b0 register timer b1 register timer b2 register timer a1 mode register timer a0 mode register timer a2 mode register timer a3 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register 1 watchdog timer register particular function select register 0 particular function select register 1 debug control register 0 int 3 interrupt control register uart0 transmit interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b2 interrupt control register reserved area (note) watchdog timer frequency select register debug control register 1 int 4 interrupt control register uart1 transmit interrupt control register timer a2 interrupt control register timer b1 interrupt control register reserved area (note) address comparison register 0 address comparison register 1 particular function select register 2 reserved area (note) note: do not write to this address. uart0 transmit/receive control register 0 up-down register 0 processor mode register 0 a-d conversion interrupt control register uart0 receive interrupt control register reserved area (note) reserved area (note) reserved area (note) reserved area (note) count start register 1 one-shot start register 1 reserved area (note) reserved area (note)
11 m37906f8cfp, M37906F8CSP preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 3 location of sfrs (2) 0000c0 16 0000c1 16 0000c2 16 0000c3 16 0000c4 16 0000c5 16 0000c6 16 0000c7 16 0000c8 16 0000c9 16 0000ca 16 0000cb 16 0000cc 16 0000cd 16 0000ce 16 0000cf 16 0000d0 16 0000d1 16 0000d2 16 0000d3 16 0000d4 16 0000d5 16 0000d6 16 0000d7 16 0000d8 16 0000d9 16 0000da 16 0000db 16 0000dc 16 0000dd 16 0000de 16 0000df 16 0000e0 16 0000e1 16 0000e2 16 0000e3 16 0000e4 16 0000e5 16 0000e6 16 0000e7 16 0000e8 16 0000e9 16 0000ea 16 0000eb 16 0000ec 16 0000ed 16 0000ee 16 0000ef 16 0000f0 16 0000f1 16 0000f2 16 0000f3 16 0000f4 16 0000f5 16 0000f6 16 0000f7 16 0000f8 16 0000f9 16 0000fa 16 0000fb 16 0000fc 16 0000fd 16 0000fe 16 0000ff 16 0000a0 16 0000a1 16 0000a2 16 0000a3 16 0000a4 16 0000a5 16 0000a6 16 0000a7 16 0000a8 16 0000a9 16 0000aa 16 0000ab 16 0000ac 16 0000ad 16 0000ae 16 0000af 16 0000b0 16 0000b1 16 0000b2 16 0000b3 16 0000b4 16 0000b5 16 0000b6 16 0000b7 16 0000b8 16 0000b9 16 0000ba 16 0000bb 16 0000bc 16 0000bd 16 0000be 16 0000bf 16 reserved area (note) reserved area (note) reserved area (note) waveform output mode register serial i/o pin control register 000080 16 000081 16 000082 16 000083 16 000084 16 000085 16 000086 16 000087 16 000088 16 000089 16 00008a 16 00008b 16 00008c 16 00008d 16 00008e 16 00008f 16 000090 16 000091 16 000092 16 000093 16 000094 16 000095 16 000096 16 000097 16 000098 16 000099 16 00009a 16 00009b 16 00009c 16 00009d 16 00009e 16 00009f 16 address (hexadecimal notation) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) d-a control register d-a register 0 d-a register 1 note: do not write to this address. clock control register 0 reserved area (note) reserved area (note) address (hexadecimal notation) reserved area (note) reserved area (note) dead-time timer three-phase output data register 0 three-phase output data register 1 position-data-retain function control register port p2 pin function control register reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) comparator result register 0 reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) timer a5 interrupt control register timer a6 interrupt control register timer a8 interrupt control register timer a9 interrupt control register timer a7 interrupt control register int 5 interrupt control register int 6 interrupt control register int 7 interrupt control register up-down register 1 timer a5 register timer a6 register timer a7 register timer a8 register timer a9 register timer a0 1 register timer a1 1 register timer a2 1 register timer a5 mode register timer a6 mode register timer a7 mode register timer a8 mode register timer a9 mode register reserved area (note) comparator function select register 0 reserved area (note) external interrupt input read-out register reserved area (note) reserved area (note) reserved area (note) reserved area (note) flash memory control register
m37906f8cfp, M37906F8CSP 16-bit cmos microcomputer mitsubishi microcomputers preliminar y n otice: this is not a final specification. som e param etric lim its are subject to change. 12 flash memory mode these microcomputers contain the flash memory; and single-power- supply reprogramming is available to this. these microcomputers have the following three modes, enabling reading/programming/era- sure for the flash memory: ?flash memory parallel i/o mode and flash memory serial i/o mode, where the flash memory is handled by using an external pro- grammer. ?cpu reprogramming mode, where the flash memory is handled by the central processing unit (cpu). as shown in figure 4, the flash memory is divided into several blocks, and erasure per block is possible. fig. 4 m37906f8cfp, M37906F8CSP: block configuration of internal flash memory this internal flash memory has the boot rom area storing the repro- gramming control software for reprogramming in the cpu repro- gramming mode and flash memory serial i/o mode, as well as the user rom area storing a certain control software for the normal op- eration in the microcomputer mode. although our reprogramming control firmware for the flash memory serial i/o mode has been stored into this boot rom area on ship- ment, the user-original reprogramming control software which is more appropriate for the users system is reprogrammable into this area, instead. note that the reprogramming for the boot rom area is enabled only in the flash memory parallel i/o mode. 28 kbytes 16 kbytes 8 kbytes 8 kbytes 001000 16 001000 16 00ffff 16 007fff 16 008000 16 00bfff 16 00c000 16 00ffff 16 00e000 16 00dfff 16
16-bit cmos microcomputer m37906f8cfp, M37906F8CSP mitsubishi microcomputers preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 13 flash memory parallel i/o mode the flash memory parallel i/o mode is used to manipulate the inter- nal flash memory with a parallel programmer. this parallel program- mer uses the software commands listed in table 1 to do the flash memory manipulations, such as read/programming/erase opera- tions. table 1. software commands (flash memory parallel i/o mode) software command read array read status register clear status register programming block erase erase all block user rom area and boot rom area the user rom area and boot rom area can be reprogrammed in the flash memory parallel i/o mode. the programming and block erase operations can be performed only to these areas. the boot rom area, 8 kbytes in size, is assigned to addresses 0000 16 1fff 16 , so that programming and block erase operations can be performed only to this area. (access to any address out of this area is prohibited). the erasable block in the boot rom area is only one block, consist- ing of 8 kbytes. the reprogramming control firmware to be used in the flash memory serial i/o mode has been stored to this boot rom area on our shipment. therefore, do not reprogram the boot rom area if the user uses the flash memory serial i/o mode. do not program to addresses ff90 16 to ff9f 16 because this area is the reserved area for the programmer. note that, when the boot rom area is read out from the cpu in the cpu reprogramming mode, described later, its addresses will be shifted to e000 16 ffff 16 . addresses ff90 16 to ff9f 16 are the reserved area for the parallel programmer. therefore, when the user uses the flash memory paral- lel i/o mode, do not program to this area.
m37906f8cfp, M37906F8CSP 16-bit cmos microcomputer mitsubishi microcomputers preliminar y n otice: this is not a final specification. som e param etric lim its are subject to change. 14 flash memory serial i/o mode in the flash memory serial i/o mode, addresses, data, and software commands, which are required to read/program/erase the internal flash memory, are serially input and output with a fewer pins and the dedicated serial programmer. in this mode, being different from the flash memory parallel i/o mode, the cpu controls reprogramming of the flash memory (using the cpu reprogramming mode), serial input of the reprogramming data, etc. the reprogramming control firmware for the flash memory serial i/o mode has been stored in the boot rom area on shipment of the product from us. note that, then, the flash memory serial i/o mode will become unavailable if the boot rom area has been repro- grammed in the flash memory parallel i/o mode. note that, also, this reprogramming control firmware for the flash memory serial i/o mode is subject to change. figures 5 and 6 show the pin connections in the flash memory serial i/o mode. the three pins, sclk, sda, and busy, are used to input and output serial data. the sclk pin is the input pin of external transfer clocks. the sda pin is the i/o pin of transmit and receive data, and its output acts as the n-channel open-drain output. to the sda pin, connect an exter- nal pullup resistor (about 1 k ? ). the busy pin is the output pin of the busy flag (cmos output) and goes h during busy periods owing to a certain operation, such as transmit, receive, erase, program- ming, etc. transmit and receive data are serially transferred 8 bits at a time. in the flash memory serial i/o mode, only the user rom area can be reprogrammed; the boot rom area is not accessible. addresses ff90 16 to ff9f 16 are the reserved area for the serial programmer. therefore, when the user uses the flash memory serial i/o mode, do not program to this area.
16-bit cmos microcomputer m37906f8cfp, M37906F8CSP mitsubishi microcomputers preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 15 fig. 5 pin connection of m37906f8cfp in flash memory serial i/o mode (outline: 42p2r-e) outline 42p2r-e avss 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 v ref p7 4 /an 4 /da 1 /int 3 /rtp trg0 p7 3 /an 3 /da 0 p7 2 /an 2 p7 1 /an 1 p7 0 /an 0 p6 5 /ta2 in /u/rtp1 1 p6 4 /ta2 out /v/rtp1 0 md0 v cont vcc avcc p1 2 /r x d 0 p1 3 /t x d 0 p1 6 /r x d 1 p1 7 /t x d 1 p2 0 /ta4 out p2 1 /ta4 in p2 2 /ta9 out p2 3 /ta9 in p2 4 (/tb0 in ) p2 5 (/tb1 in ) p2 6 (/tb2 in ) md1 x out x in vss p6 3 /ta1 in /w/rtp0 3 p6 2 /ta1 out /u/rtp0 2 p6 1 /ta0 in /v/rtp0 1 p6 0 /ta0 out /w/rtp0 0 p6out cut /int 4 reset p2 7 (/int 3 /rtp trg0 ) p1 5 /cts 1 /clk 1 p1 4 /cts 1 /rts 1 p1 1 /cts 0 /clk 0 p1 0 /cts 0 /rts 0 p5 7 /int 7 /tb2 in /idu p5 6 /int 6 /tb1 in /idv p5 5 /int 5 /tb0 in /idw notes 1: allocation of pins tb0 in to tb2 in and int 3 /rtp trg0 can be switched by software. 2: connected to the oscillation circuit. 3: recommended to be connected with v cc via a resistor. : connected to a serial programmer. (note 3) (note 1) md1 busy sda sclk (note 2) (note 1) (note 1) v cc v ss reset m37906f8cfp
m37906f8cfp, M37906F8CSP 16-bit cmos microcomputer mitsubishi microcomputers preliminar y n otice: this is not a final specification. som e param etric lim its are subject to change. 16 fig. 6 pin connection of M37906F8CSP in flash memory serial i/o mode (outline: 42p4b) avss 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 v ref p7 4 /an 4 /da 1 /int 3 /rtp trg0 p7 3 /an 3 /da 0 p7 2 /an 2 p7 1 /an 1 p7 0 /an 0 p6 5 /ta2 in /u/rtp1 1 p6 4 /ta2 out /v/rtp1 0 md0 v cont vcc avcc p1 2 /r x d 0 p1 3 /t x d 0 p1 6 /r x d 1 p1 7 /t x d 1 p2 0 /ta4 out p2 1 /ta4 in p2 2 /ta9 out p2 3 /ta9 in p2 4 (/tb0 in ) p2 5 (/tb1 in ) p2 6 (/tb2 in ) md1 x out x in vss p6 3 /ta1 in /w/rtp0 3 p6 2 /ta1 out /u/rtp0 2 p6 1 /ta0 in /v/rtp0 1 p6 0 /ta0 out /w/rtp0 0 reset p2 7 (/int 3 /rtp trg0 ) p1 5 /cts 1 /clk 1 p1 4 /cts 1 /rts 1 p1 1 /cts 0 /clk 0 p1 0 /cts 0 /rts 0 p5 7 /int 7 /tb2 in /idu p5 6 /int 6 /tb1 in /idv p5 5 /int 5 /tb0 in /idw (note 1) md1 busy sda sclk (note 2) (note 1) (note 1) v cc v ss reset (note 3) p6out cut /int 4 notes 1: allocation of pins tb0 in to tb2 in and int 3 /rtp trg0 can be switched by software. 2: connected to the oscillation circuit. 3: recommended to be connected with v cc via a resistor. : connected to a serial programmer. M37906F8CSP outline 42p4b
16-bit cmos microcomputer m37906f8cfp, M37906F8CSP mitsubishi microcomputers preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 17 cpu reprogramming mode the cpu reprogramming mode is used to perform the operations for the internal flash memory (reading, programming, erasing) under control of the cpu. in this mode, only the user rom area can be reprogrammed; the boot rom area cannot be reprogrammed. the user-original reprogramming control software for the cpu repro- gramming mode can be stored in either the user rom area or the boot rom area. because the cpu cannot read out the flash memory in the cpu re- programming mode, the above software must be transferred to the internal ram in advance to be executed. boot mode the user-original reprogramming control software for the cpu repro- gramming mode must be stored into the user rom area or the boot rom area in the flash memory parallel i/o mode in advance. (if this program has been stored into the boot rom area, the flash memory serial i/o mode will become unavailable). note that addresses of the boot rom area depend on the accessing ways to the boot rom area, when accessing in the flash memory parallel i/o mode, these addresses will be shifted to 0000 16 to 1fff 16 . on the other hand, when accessing with the cpu, these ad- dresses will be shifted to e000 16 to ffff 16 . reset removal with both of the md0 and md1 pins held ??invokes the normal microcomputer mode, and the cpu operates using the control software stored in the user rom area. in this case, the boot rom area is not accessible. removing reset with the md0 pin held ??and the md1 pin ?? the cpu starts its operation using the reprogramming control software stored in the boot rom area. this mode is called the boot mode. the reprogramming control software in the boot rom area can also re- program the user rom area. after reset removal, be sure not to change the status at pins md0 and md1. fig. 7 bit configuration of flash memory control register flash memory control register ry/by status bit 0: busy (programming or erasing is active.) 1: ready cpu reprogramming mode select bit (note 2) 0: normal mode (software commands are ignored.) 1: cpu reprogramming mode (software commands are acceptable.) flash memory reset bit (note 3) 0: normal operation 1: reset user rom area select bit (note 4) (valid only in the boot mode.) 0: boot rom area access 1: user rom area access notes 1: the contents of the flash memory control register after reset is removed are xx000001 . 2: to set 1 , writing of 0 to bit 1 and subsequent writing of 1 to bit 1 are necessary. writing to bit 1 must be performed by the user-original reprogramming control software in the internal ram. 3: this bit is valid only when bit 1 = 1 . before setting this bit to 0 , be sure to confirm that bit 0 = 1 after setting this bit to 1 (reset). this bit 3 must be controlled with bit 1 = 1 . 4: writing to bit 5 must be performed by the user-original reprogramming control software in the internal ram. 7654321 0 address 9e 16
m37906f8cfp, M37906F8CSP 16-bit cmos microcomputer mitsubishi microcomputers preliminar y n otice: this is not a final specification. som e param etric lim its are subject to change. 18 function overview (cpu reprogramming mode) the cpu reprogramming mode is available in the single-chip mode, memory expansion mode, and boot mode to reprogram the user rom area only. in the cpu reprogramming mode, the cpu erases, programs, and reads the internal flash memory by writing software commands. note that the user-original reprogramming control software must be trans- ferred to the internal ram in advance to be executed. the cpu reprogramming mode becomes active when 1 is written into the flash memory control register s bit 1 (the cpu reprogram- ming mode select bit) shown in figure 7, and software commands become acceptable. in the cpu reprogramming mode, software commands and data are all written to and read from even addresses (note that address a 0 in byte addresses = 0 .) 16 bits at a time. therefore, a software com- mand consisting of 8 bits must be written to an even address; there- fore, any command written to an odd address will be invalid. since the write data at the 2nd cycle of a programming command consists of 16 bits, this data must be written to even and odd addresses. the seaquencer in the flash memory controls the erase and pro- gramming operations. what the status of the seaquencer operation is and whether the programming or erase operation has been com- pleted normally or terminated by an error can be examined by read- ing the flash memory control register. figure 7 shows the bit configuration of the flash memory control reg- ister. bit 0 (the ry/by status bit) is a read-only bit for indicating the sea- quencer operation. this bit goes to 0 (busy) while the automatic programming/erase operation is active and goes to 1 (ready) dur- ing the other operations. bit 1 serves as the cpu reprogramming mode select bit. writing of 1 to this bit selects the cpu reprogramming mode, and software commands will be acceptable. because the cpu cannot directly ac- cess the internal flash memory in the cpu reprogramming mode, writing to this bit 1 must be performed by the user-original repro- gramming control software which has been transferred to the inter- nal ram in advance. to set bit 1 to 1 , it is necessary to write 0 and 1 to this bit 1 successively. on the other hand, to clear this bit to 0 , it is sufficient only to write 0 . bit 3 (the flash memory reset bit) resets the control circuit of the in- ternal flash memory and is used when the cpu reprogramming mode is terminated or when an abnormal access to the flash memory happens. writing of 1 to bit 3 with the cpu reprogramming mode select bit = 1 preforms the reset operation. to remove the reset, write 0 to bit 3 after confirming bit 0 (the ry/by status bit) be- comes 1 . bit 5 serves as the user rom area select bit and is valid only in the boot mode. setting this bit to 1 in the boot mode switches an acces- sible area from the boot rom area to the user rom area. to use the cpu reprogramming mode in the boot mode, set this bit to 1 . note that when the microcomputer is booted up in the user rom area, only the user rom area is accessible and bit 5 is invalid; on the other hand, when the microcomputer is in the boot mode, bit 5 is valid in- dependent of the cpu reprogramming mode. to rewrite bit 5, ex- ecute the user-original reprogramming control software transferred to the internal ram in advance. figure 8 shows the cpu reprogramming mode set/termination flow- chart, and be sure to follow this flowchart. as shown in note 1 of fig- ure 8, before selecting the cpu reprogramming mode, set 0 to the processor mode register 1 s bit 7 (the internal rom bus cycle select bit) and set flag i to 1 to avoid an interrupt request input. when a watchdog timer interrupt request is generated in the cpu reprogramming mode, when an input to the reset pin is l , or when the software reset is performed, the flash memory control cir- cuit and flash memory control register will be reset. when the flash memory is reset during the erase or programming operation, this operation is cancelled and the target block s data will be invalid. just before writing a software command related to the erase/programming operation, be sure to write to the watchdog timer. in the cpu reprogramming mode, be sure not to use the stp and wit instructions.
16-bit cmos microcomputer m37906f8cfp, M37906F8CSP mitsubishi microcomputers preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 19 fig. 8 cpu reprogramming mode set/termination flowchart software commands table 2 lists the software commands. by writing a software command after the cpu reprogramming mode select bit has been set to 1 , erasing, programming, etc. can be specified. note that, at software commands input, the high-order byte (d 8 d 15 ) is ignored. (except for the write data at the 2nd cycle of a programming command.) software commands are explained as below. read array command (ff 16 ) by writing command code ff 16 at the 1st bus cycle, the microcom- puter enters the read array mode. if an address to be read is input in the next or the following bus cycles, the contents at the specified ad- dress are output to the data bus (d 0 to d 15 ) in a unit of 16 bits. the read array mode is maintained until writing of another software command. read status register command (70 16 ) writing command code 70 16 at the 1st bus cycle outputs the con- tents of the status register to the data bus (d 0 -d 7 ) by a read at the 2nd bus cycle. the status register is explained later. clear status register command (50 16 ) this command clears two status bits (sr.4, 5) each of which is set to 1 to indicate that the operation has been terminated by an error. to clear these bits, write command code 50 16 at the 1st bus cycle. programming command (40 16 ) this command facilitates programming of 1 word (2 bytes) at a time. to initiate programming, write command code 40 16 at the 1st bus cycle; when write data is written in a unit of 16 bits at the 2nd bus cycle, the address is specified at the same time. upon completion of data writing, automatic programming (data programming and verifi- cation) operation is started. the completion of the automatic programming operation is con- firmed by a read of the flash memory control register. the ry/by sta- tus bit of the flash memory control register goes 0 during the automatic programming operation; and also, it goes 1 after the end of it. before execution of the next command, be sure to confirm that the ry/by status bit is set to 1 (ready). during the automatic pro- gramming operation, writing of commands and access to the flash memory must not be performed. when programming continuously, the programming command can be executed with the read status register mode kept if there is no programming error. simultaneously with start of the automatic pro- gramming, the read status register mode is automatically active. in this case, the read status register mode is retained until the next read array command (ff 16 ) is written or until the reset is performed by using the flash memory reset bit. reading out the status register after the automatic programming op- eration is completed reports the result of it. for details, refer to the section on the status register. figure 9 shows an example of the programming flowchart. additional programming to any word that has already been pro- grammed is prohibited. completed start read array command is executed, or reset is performed by setting the flash memory reset bit. (writing of 1 writing of 0 ) (note 2) single-chip mode, memory expansion mode, or boot mode the processor mode register 1 is set (note 1) . flag i is set to 1 . operations such as erasing, programming are executed by using software commands. jump to the above software in the internal ram. (the operations shown below will be executed by the above software in this ram.) the user-original reprogramming control software for the cpu reprogramming mode is transferred to the internal ram. (only in the boot mode.) writing of 0 to user rom area select bit (note 3) . writing of 0 to the cpu reprogramming mode select bit. (only in the boot mode.) the user rom area select bit is set to 1 . writing of 1 to the cpu reprogramming mode select bit. (writing of 0 writing of 1 ) notes 1: the processor mode register 1 s bit 7 (address 5f 16 , the internal rom bus cycle select bit) must be 0 (bus cycle = 3 ). 2: to terminate the cpu reprogramming mode after the erase and programming operations have been completed, be sure to execute the read array command or perform the flash memory reset operation. 3: this bit may remain 1 . however, if this bit is 1 , the user rom area access is specified.
m37906f8cfp, M37906F8CSP 16-bit cmos microcomputer mitsubishi microcomputers preliminar y n otice: this is not a final specification. som e param etric lim its are subject to change. 20 table 2. software commands (cpu reprogramming mode) command read array read status register clear status register programming block erase erase all block address x (note 2) x x x x x ff 16 70 16 50 16 40 16 20 16 20 16 1st cycle 2nd cycle notes 1: at software commands input, the high-order byte of data (d 8 d 15 ) is ignored. 2: x = an arbitrary address in the user rom area. (note that a 0 = 0 .) 3: srd = status register data 4: wa = write address, wd = write data (16 bits). 5: block address: the maximum address of each block must be input. note that address a 0 = 0 . mode write write write write write write (d 0 to d 7 ) data address x wa (note 4) ba (note 5) x srd (note 3) wd (note 4) d0 16 20 16 mode read write write write block erase command (20 16 /d0 16 ) writing command code 20 16 at the 1st bus cycle and writing confir- mation command code d0 16 and the maximum address of the block (note that address a 0 = 0 .) at the subsequent 2nd bus cycle initiate the automatic erase (erasing and erase verification) operation for the specified block. the completion of the automatic erase operation is confirmed by a read of the flash memory control register. the ry/by status bit of the flash memory control register goes 0 simultaneously with start of the automatic erase operation; and also, it goes 1 simultaneously with completion of it. before execution of the next command, be sure to confirm that the ry/by status bit is set to 1 (ready). during the automatic erase operation, writing of commands and access to the flash memory must not be performed. simultaneously with start of the automatic erase, the read status reg- ister mode is automatically active. in this case, the read status regis- ter mode is retained until the next read array command (ff 16 ) is written or until the reset is performed by using the flash memory re- set bit. reading out the status register after the automatic erase operation is completed reports the result of it. for details, refer to the section on the status register. figure 10 shows an example of the block erase flowchart. data
16-bit cmos microcomputer m37906f8cfp, M37906F8CSP mitsubishi microcomputers preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 21 fig. 9 programming flowchart fig. 10 block erase flowchart start write 40 16 write, address, data flash memory control register read full status check programming completed no yes ry/by status bit = 1? write 20 16 write d0 16 , flash memory control register read full status check block erase completed no yes block address start ry/by status bit = 1? erase all block command (20 16 /20 16 ) writing command code 20 16 at the 1st bus cycle and writing com- mand code 20 16 at the subsequent 2nd bus cycle initiate the con- tinuous block erase (chip erase) operations for all the blocks. the completion of the chip erase operation, as well as of the block erase operation, is confirmed by a read of the flash memory control register. the result of the automatic erase operation is also reported by a read of the status register. during the automatic erase operation (when the ry/by status bit = 0 ), writing of commands and access to the flash memory must not be performed. status register the status register is used to indicate whether the programming/ erase operation has been completed normally or terminated by an error. by writing the read status register command (70 16 ), the con- tents of the status register can be read out; by writing the clear sta- tus register command (50 16 ), the contents of the status register can be cleared. table 3 lists the definition of each bit of the status register. the status register outputs 80 16 after reset is removed. the status of each bit is described below.
m37906f8cfp, M37906F8CSP 16-bit cmos microcomputer mitsubishi microcomputers preliminar y n otice: this is not a final specification. som e param etric lim its are subject to change. 22 erase status bit (sr.5) this bit reports the status of the automatic erase operation. this bit is set to 1 if an erase error occurs and returns to 0 if the clear sta- tus register command (50 16 ) is written. programming status bit (sr.4) this bit reports the status of the automatic programming operation. this bit is set to 1 if a programming error occurs and returns to 0 if the clear status register command (50 16 ) is written. under the condition that any of sr.5, sr.4 = 1 , none of the pro- gramming, block erase, and erase all block commands can be ac- cepted. before execution of these commands, execute the clear status register command (50 16 ), in advance, to clear these status bits. both of sr.4, sr.5 are set to 1 under the following conditions (command sequence error): (1) when data other than d0 16 and ff 16 is written to the data in the 2nd bus cycle of the block erase command (20 16 /d0 16 ) (2) when data other than 20 16 and ff 16 is written to the data in the 2nd bus cycle of the erase all block command (20 16 /20 16 ) note that, writing of ff 16 forces the microcomputer into the read array mode. simultaneously with this, the command written in the 1st bus cycle will be canceled. full status check the full status check reports the results of the erase or programming operation. figure 11 shows the full status check flowchart and actions to be taken if an error has occurred. terminated normally. terminated normally. terminated by error. terminated by error. table 3. bit definition of status register sr.7 (d 7 ) sr.6 (d 6 ) sr.5 (d 5 ) sr.4 (d 4 ) sr.3 (d 3 ) sr.2 (d 2 ) sr.1 (d 1 ) sr.0 (d 0 ) reserved reserved erase status programming status reserved reserved reserved reserved symbol status definition 1 0
16-bit cmos microcomputer m37906f8cfp, M37906F8CSP mitsubishi microcomputers preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 23 fig. 11 full status check flowchart and actions to be taken if an error has ocurred ac electrical characteristics (v cc = 5 v ?0.5 v, ta = 0 to 60 ?, f(f sys ) = 20 mhz (note)) symbol parameter limits unit min. typ. max. v cc power source current (at read) v cc power source current (at write) v cc power source current (at programming) v cc power source current (at erasing) 48 48 54 54 dc electrical characteristics (v cc = 5 v ?0.5 v, ta = 0 to 60 ?, f(f sys ) = 20 mhz (note)) limits of v ih , v il , v oh , v ol , i ih , and i il for each pin are the same as those in the microcomputer mode. note: f(f sys ) indicates the system clcok (fsys) frequency. ma ma ma ma parameter 256-byte programming time block erase time erase all block time limits unit min. typ. max. 4 0.6 0.6 ? n 40 8 8 ? n ms s s n = number of blocks to be erased i cc1 i cc2 i cc3 i cc4 30 the limits of parameters other than the above are same as those in the microcomputer mode. note: f(f sys ) indicates the system clock (fsys) frequency. status register read sr.4 = 1 no command sequence error yes sr.5 = 0? yes block erase error no sr.4 = 0? yes programming error no end (block erase, programming) and sr.5 = 1 ? ? execute the clear status register command (50 16 ) to clear the status register. ? confirm whether the command has correctly been input or not; and then, start the operation again. perform the block erase operation again. if an error occurs even after the above operation is performed, the block cannot be used. perform the programming operation again. if an error occurs even after the above operation is performed, the word cannot be used. note: under the condition that any of sr.5 and sr.4 = 1 , none of the programming, block erase, and erase all block commands can be accepted. before execution of these commands, execute the clear status register command (50 16 ) in advance.
24 m37906f8cfp, M37906F8CSP preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers unit v v v v v v ma ma ma ma ma ma mhz mhz max. 5.5 vcc 0.2 v cc ?0 ? 10 20 5 15 20 20 parameter power source voltage analog power source voltage power source voltage analog power source voltage high-level input voltage p1 0 ?1 7 , p2 0 ?2 7 , p5 5 ?5 7 , p6 0 ?6 5 , p7 0 ?7 4 , p6out cut , x in , reset, md0, md1 low-level input voltage p1 0 ?1 7 , p2 0 ?2 7 , p5 5 ?5 7 , p6 0 ?6 5 , p7 0 ?7 4 , p6out cut , x in , reset, md0, md1 high-level peak output current p1 0 ?1 7 , p2 0 ?2 7 , p5 5 ?5 7 , p6 0 ?6 5 , p7 0 ?7 4 high-level average output current p1 0 ?1 7 , p2 0 ?2 7 , p5 5 ?5 7 , p6 0 ?6 5 , p7 0 ?7 4 low-level peak output current p1 0 ?1 7 , p2 0 ?2 7 , p5 5 ?5 7 , p7 0 ?7 4 low-level peak output current p6 0 ?6 5 low-level average output current p1 0 ?1 7 , p2 0 ?2 7 , p5 5 ?5 7 , p7 0 ?7 4 low-level average output current p6 0 ?6 5 external clock input frequency (note 1) system clock frequency symbol v cc av cc v ss av ss v ih v il i oh(peak) i oh(avg ) i ol(peak) i ol(peak) i ol(avg) i ol(avg) f(x in ) f(f sys ) parameter power source voltage analog power source voltage input voltage p1 0 ?1 7 , p2 0 ?2 7 , p5 5 ?5 7 , p6 0 ?6 5 , p7 0 ?7 4 , p6out cut , v cont , v ref , x in , reset, byte, md0, md1 output voltage p1 0 ?1 7 , p2 0 ?2 7 , p5 5 ?5 7 , p6 0 ?6 5 , p7 0 ?7 4 , x out power dissipation operating ambient temperature storage temerature symbol v cc av cc v i v o p d t opr t stg absolute maximum ratings recommended operating conditions (vcc = 5 v, ta = ?0 to 85 ?, unless otherwise noted) notes 1: when using the pll frequency multiplier, be sure that f(f sys ) = 20 mhz or less. 2: the average output current is the average value of an interval of 100 ms. 3: the sum of i ol(peak) must be 110 ma or less, the sum of i oh(peak) must be 80 ma or less. unit v v v v mw ? ? ratings ?.3 to 6.5 ?.3 to 6.5 ?.3 to v cc +0.3 ?.3 to v cc +0.3 300 ?0 to 85 ?0 to 150 limits min. 4.5 0.8 vcc 0 typ. 5.0 v cc 0 0
25 m37906f8cfp, M37906F8CSP preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers unit v v v v v a a v ma a f(f sys ) = 20 mhz. cpu is active. ta = 25 c when clock is inactive. ta = 85 c when clock is inactive. test conditions i oh = ?0 ma i ol = 10 ma v i = 5.0 v v i = 0 v when clock is inactive. parameter high-level output voltage p1 0 ?1 7 , p2 0 ?2 7 , p5 5 ?5 7 , p6 0 ?6 5 , p7 0 ?7 4 low-level output voltage p1 0 ?1 7 , p2 0 ?2 7 , p5 5 ?5 7 , p6 0 ?6 5 , p7 0 ?7 4 hysteresis ta0 in ?a2 in , ta4 in , ta9 in , ta0 out ?a2 out , ta4 out , ta9 out , tb0 in ?b2 in , int 3 ?nt 7 , cts 0 , cts 1 , clk 0 , clk 1 , rxd 0 , rxd 1 , rtp trg0 , p6out cut hysteresis reset hysteresis x in high-level input current p1 0 ?1 7 , p2 0 ?2 7 , p5 5 ?5 7 , p6 0 ?6 5 , p7 0 ?7 4 , p6out cut , x in , reset, md0, md1 low-level input current p1 0 ?1 7 , p2 0 ?2 7 , p5 5 ?5 7 , p6 0 ?6 5 , p7 0 ?7 4 , p6out cut , x in , reset, md0, md1 ram hold voltage power source current symbol v oh v ol v t+ vt v t+ vt v t+ vt i ih i il v ram i cc dc electrical characteristics (vcc = 5 v, vss = 0 v, ta = ?0 to 85 ?, f(f sys ) = 20 mhz) min. 3 0.4 0.5 0.1 2 limits typ. 25 max. 2 1 1.5 0.3 5 ? 50 1 20 output-only pins are open, and the other pins are con- nected to vss or vcc. an external square-waveform clock is input. (pin x out is open.) the pll frequency multiplier is inac- tive.
26 m37906f8cfp, M37906F8CSP preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers resolution absolute accuracy ladder resistance conversion time reference voltage analog input voltage r ladder t conv v ref v ia v ref = v cc v ref = v cc v ref = v cc f(f sys ) 20 mhz max. a-d converter characteristics (v cc = av cc = 5 v ?0.5 v, v ss = av ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) unit parameter symbol test conditions limits min. 10-bit resolution mode 8-bit resolution mode comparater 10-bit resolution mode 8-bit resolution mode comparater 5 5.9 2.45 (note) 0.7 (note) 2.7 0 10 ?3 ?2 ?40 v cc v ref bits v lsb lsb mv k ? s v v note: this is applied when a-d conversion freguency ( ad ) = f 1 ( ). d-a converter characteristics (v cc = 5 v, v ss = av ss = 0 v, v ref = 5 v, t a = ?0 to 85 ?, unless otherwise noted) unit parameter symbol limits typ. min. max. test conditions resolution absolute accuracy set time output resistance reference power source input current t su r o i vref (note) 2 3.5 8 ?1.0 3 4.5 3.2 bits % s k ? ma note: the test conditions are as follows: ?one d-a converter is used. ?the d-a register value of the unused d-a converter is ?0 16 . ?the reference power source input current for the ladder resistance of the a-d converter is excluded. s reset input low-level pulse width t w(resetl) symbol parameter min. limits unit reset input reset input timing requirements (v cc = 5 v ?0.5 v, v ss = 0v, ta = ?0 to 85 ?, unless otherwise noted) 10 max. typ. reset input t w(resetl) a-d converter comparator 256 1 v ref typ.
27 m37906f8cfp, M37906F8CSP preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers t c(ta) t w(tah) t w(tal) f(f sys ) 20 mhz f(f sys ) 20 mhz f(f sys ) 20 mhz peripheral device input/output timing (v cc = 5 v?.5 v, v ss = 0 v, t a = ?0 to 85 ?, f(f sys ) = 20 mhz unless otherwise noted) ? for limits depending on f(f sys ), their calculation formulas are shown below. also, the values at f(f sys ) = 20 mhz are shown in ( ). timer a input (up-down input and count input in event counter mode) t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in -up) symbol tai out input cycle time tai out input high-level pulse width tai out input low-level pulse width tai out input setup time tai out input hold time parameter limits min. 2000 1000 1000 400 400 max. ns ns ns ns ns unit timer a input (external trigger input in pulse width modulation mode) t w(tah) t w(tal) symbol tai in input high-level pulse width tai in input low-level pulse width parameter min. 80 80 limits max. ns ns unit limits symbol parameter min. max. unit 8 10 9 f(f sys ) (400) tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width ns ns ns 80 80 timer a input (external trigger input in one-shot pulse mode) limits symbol parameter min. max. unit 16 10 9 f(f sys ) 8 10 9 f(f sys ) 8 10 9 f(f sys ) (800) (400) (400) t c(ta) t w(tah) t w(tal) tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width ns ns ns timer a input (gating input in timer mode) note : the tai in input cycle time requires 4 or more cycles of a count source. the tai in input high-level pulse width and the tai in input low-level pulse width respectively require 2 or more cycles of a count source. the limits in this table are applied when the count source = f 2 at f(f sys ) 20 mhz. timer a input (count input in event counter mode) t c(ta) t w(tah) t w(tal) symbol tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width parameter min. 80 40 40 limits max. ns ns ns unit f(f sys ) 20 mhz
28 m37906f8cfp, M37906F8CSP preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers t c(ta) t su(ta jin -ta jout ) t su(ta jout -ta jin ) symbol parameter min. 800 200 200 limits max. ns ns ns unit timer a input (two-phase pulse input in event counter mode) taj in input cycle time taj in input setup time taj out input setup time t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(t in -up) t su(up-t in ) t su(taj in -taj out ) t su(taj out -taj in ) t su(taj in -taj out ) t su(taj out -taj in ) t c(ta) ?gating input in timer mode ?count input in event counter mode ?external trigger input in one-shot pulse mode ?external trigger input in pulse width modulation mode tai in input tai out input (up-down input) tai out input (up-down input) ?up-down and count input in event counter mode tai in input (when count by falling) tai in input (when count by rising) taj in input taj out input ?two-phase pulse input in event counter mode test conditions ?v cc = 5 v 0.5 v, ta = ?0 to 85 c ?input timing voltage : v il = 1.0 v, vih = 4.0 v
29 m37906f8cfp, M37906F8CSP preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers f(f sys ) 20 mhz f(f sys ) 20 mhz f(f sys ) 20 mhz f(f sys ) 20 mhz f(f sys ) 20 mhz f(f sys ) 20 mhz t c(tb) t w(tbh) t w(tbl) t c(tb) t w(tbh) t w(tbl) timer b input (count input in event counter mode) symbol tbi in input cycle time (one edge count) tbi in input high-level pulse width (one edge count) tbi in input low-level pulse width (one edge count) tbi in input cycle time (both edge count) tbi in input high-level pulse width (both edge count) tbi in input low-level pulse width (both edge count) parameter limits min. 80 40 40 160 80 80 max. ns ns ns ns ns ns unit limits symbol parameter min. max. unit 16 10 9 f(f sys ) 8 10 9 f(f sys ) 8 10 9 f(f sys ) (800) (400) (400) t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width ns ns ns timer b input (pulse period measurement mode) note: the tbi in input cycle time requires 4 or more cycles of a count source. the tbi in input high-level pulse width and the tbi in input low-level pulse width respectively require 2 or more cycles of a count source. the limits in this table are applied when the count source = f 2 at f(f sys ) 20 mhz. limits symbol parameter min. max. unit 16 10 9 f(f sys ) 8 10 9 f(f sys ) 8 10 9 f(f sys ) (800) (400) (400) t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width ns ns ns timer b input (pulse width measurement mode) note: the tbi in input cycle time requires 4 or more cycles of a count source. the tbi in input high-level pulse width and the tbi in input low-level pulse width respectively require 2 or more cycles of a count source. the limits in this table are applied when the count source = f 2 at f(f sys ) 20 mhz. t c(ck) t w(ckh) t w(ckl) t d(c-q) t h(c-q) t su(d-c) t h(c-d) serial i/o symbol clk i input cycle time clk i input high-level pulse width clk i input low-level pulse width t x d i output delay time t x d i hold time r x d i input setup time r x d i input hold time parameter limits min. 200 100 100 0 20 90 max. 80 ns ns ns ns ns ns ns unit
30 m37906f8cfp, M37906F8CSP preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers t w(inh) t w(inl) symbol int i input high-level pulse width int i input low-level pulse width parameter min. 250 250 limits max. ns ns unit external interrupt (int i ) input t c(tb) t w(tbh) t w(tbl) t su(d-c) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c-q) t h(c-d) t h(c-q) tbi in input int i input clk i input txd i output rxd i input test conditions vcc = 5 v 0.5 v, ta = 20 to 85 c input timing voltage : v il = 1.0 v, v ih = 4.0 v output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 50 pf
31 m37906f8cfp, M37906F8CSP preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers t c t w(half) t w(h) t w(l) t r t f max. 0.55 tc 8 8 min. 50 0.45 tc 0.5 t c ?8 0.5 t c ?8 external clock input cycle time external clock input pulse width with half input-volage external clock input high-level pulse width external clock input low-level pulse width external clock input rise time external clock input fall time limits external clock input symbol parameter ns ns ns ns ns ns unit external clock input t r t f t w(l) t w(h) t w(half) x in t c test conditions vcc = 5 v 0.5 v, ta = 20 to 85 c input timing voltage : v il = 1.0 v, v ih = 4.0 v (t w(h) , t w(l) , t r , t f ) input timing voltage : 2.5 v ( t c , t w(half) ) timing requirements (v cc = 5 v?.5 v, v ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted)
32 m37906f8cfp, M37906F8CSP preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers package outline ssop42-p-450-0.80 weight(g) jedec code 0.63 eiaj package code lead material alloy 42/cu alloy 42p2r-e plastic 42pin 450mil ssop symbol min nom max a a 2 b c d e l l 1 y dimension in millimeters h e a 1 i 2 .35 0 .05 0 .13 0 .3 17 .2 8 .63 11 .3 0 .27 1 .0 2 .4 0 .15 0 .5 17 .4 8 .8 0 .93 11 .5 0 .765 1 .43 11 .4 2 .5 0 .2 0 .7 17 .6 8 .23 12 .7 0 .15 0 b 2 .5 0 0 10 e e 1 42 22 21 1 h e e d e y f a a 2 a 1 l 1 l c e b 2 e 1 i 2 recommended mount pad detail f z z 1 detail g z 1 0.75 0.9 z b g sdip42-p-600-1.78 weight(g) jedec code 4.1 eiaj package code lead material alloy 42/cu alloy 42p4b plastic 42pin 600mil sdip symbol min nom max a a 2 b b 1 b 2 c e d l dimension in millimeters a 1 0.51 3.8 0.35 0.45 0.55 0.9 1 .0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 1.778 15.24 3.0 0 15 5.5 e e 1 42 22 21 1 e c e 1 a 2 a 1 b b 1 b 2 e l a seating plane d
m37906f8cfp, M37906F8CSP preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer? application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party? rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubishi semiconductor home page (http://www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein. ?2001 mitsubishi electric corp. new publication, effective jun., 2001. specifications subject to change without notice. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making y our circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
revision history m37906f8cfp/sp datasheet rev. date description page summary (1/1) first edition some english expressions and the following are corrected: ?escription; line 3 silicon gate technology, being packaged silicon gate technology, including the internal flash memory and being packaged ?igure 7; note 3 after setting this bit to ??(reset). after setting this bit to ??(reset). this bit 3 must be controlled with bit 1 = ?? ?rogramming command (40 16 ); lines 18,19 be executed with the read status register mode kept. be executed with the read status register mode kept if there is no programming error. ?igure 11 status register error status register read 1.0 3/02/01 2.0 6/26/01 1 17 19 23

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